1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
In recent years, with the view of achieving an even higher degree of integration of a semiconductor chip, development of three-dimensional package in which semiconductor chips such as LSI are stacked in a longitudinal direction has lately been vigorously carried out. Such attempts include a technique disclosed in JP-A Laid Open No. 2000-22074. A semiconductor device described therein is shown in FIGS. 10 and 11. FIG. 10 is a schematic cross-sectional view showing a multichip stack structure based on a conventional flip chip connection. FIG. 11 is an enlarged view of the area A enclosed in a dashed circle in FIG. 10.
As shown in FIG. 10, the semiconductor device 1001 has a configuration that a second semiconductor chip 1003 is mounted on a die pad 1004 made of a metal such as nickel, for example, via a resin-based adhesive 1006, and a first semiconductor chip 1002 which serves as a controlling semiconductor chip, is stacked on the second semiconductor chip 1003. Further, the first semiconductor chip 1002, the second semiconductor chip 1003, and the die pad 1004 are sealed by a resin package 1005 constituted of a thermosetting resin such as an epoxy resin.
The first semiconductor chip 1002 includes a predetermined circuit (not shown in the drawings) and an interconnect pattern (not shown in the drawings) for driving the circuit integrally formed on a main face 1002a thereof, and also a plurality of first terminal pads 1020a electrically conductive with the circuit via the interconnect pattern. Also, the circuit and the interconnect pattern are covered with an insulating layer (not shown in the drawings) with the first terminal pads 1020a remaining exposed, so that the first terminal pads 1020a only can be electrically conductive with outer portion of the first semiconductor chip 1002.
The second semiconductor chip 1003 has a larger plan view area than the first semiconductor chip 1002, and is provided with a predetermined circuit (not shown in the drawings) integrally formed on a main face 1003 thereof, like the first semiconductor chip 1002. Also, the second semiconductor chip 1003 is provided thereon with a plurality of second terminal pads 1030a, 1031a, 1032a, and an insulating layer (not shown in the drawings) except on the second terminal pads 1030a, 1031a, 1032a. 
Referring to FIG. 11, the second terminal pad 1031a is disposed in a side region 1003b of the first semiconductor chip 1002 which is defined when the first semiconductor chip 1002 is stacked on the second semiconductor chip 1003, for electrical connection with the second terminal pad 1030a via an routing portion 1033. The routing portion 1033 is formed at the same time as formation of the terminal pads 1030a, 1031a, 1032a and the interconnect pattern. Also, the terminal pad 1031a is provided thereon with a bump 1031b, for example constituted of Au, so that the terminal pad 1031a for signals and the bump 1031b constitute a terminal portion 1031 for signals.
Here, the routing portion 1033 is formed by metal plating or vapor deposition of a metal so as to connect the respective upper faces of the second terminal pad 1030a and the terminal pad 1031a for signals. Alternatively, a metal foil formed in a predetermined shape may be stuck to constitute the routing portion 1033.
Also, the terminal portion 1031 for signals and the second terminal portion 1032 of the second semiconductor chip 1003 are respectively connected to an external connection terminal 1040 via a wire W. The external connection terminal 1040 is utilized when packaging the semiconductor device 1001 on a predetermined circuit board or the like, and includes an internal lead wire 1041 constituting an internal terminal portion sealed in inside the resin package 1005 and an external lead wire 1042 which is an external portion of the internal lead wire 1041 and projecting outside the resin package 1005.
Now, when constituting the stack structure by a technique that an anisotropic conductive resin 1007 is employed, and the resin component 1070 thereof is first melted. Then the first semiconductor chip 1002 is pressed toward the second semiconductor chip 1003, with the first terminal portion 1020 of the first semiconductor chip 1002 disposed so as to confront the second terminal portion 1030 of the second semiconductor chip 1003, thus to form the stack structure.
At this stage, since the resin component 1070 is melted and conductive balls 1071 are dispersed in the resin component 1070, the resin component 1070 located between the first terminal portion 1020 and the second terminal portion 1030 is squeezed aside, so that the conductive balls 1071 are interposed between the first terminal portion 1020 and the second terminal portion 1030. Then upon thermally setting the resin component 1070, the main face 1002a of the first semiconductor chip and the main face 1003a of the second semiconductor chip are mechanically connected. Also, since the conductive balls 1071 are interposed between the first terminal portion 1020 and the second terminal portion 1030, electrical connection is achieved between the first terminal portion 1020 and the second terminal portion 1030.
According to the configuration, the first semiconductor chip 1002 and the second semiconductor chip 1003 are disposed face to face such that the first terminal portion 1020 and the second terminal portion 1030 confront each other. Then the terminal portion 1031 for signals, which is to serve as the external terminal of the first semiconductor chip 1002, is formed in the side region of the first semiconductor chip 1002. Further, the terminal portion 1031 for signals is utilized as the wire bonding portion, thus to achieve connection to the external connection terminal 1040 via the wire W.
In addition, another example of such technique is disclosed in JP-A Laid Open No. 2000-252408. A semiconductor device disclosed therein is shown in FIG. 12. FIG. 12 is a schematic cross-sectional view showing a conventional chip-on-chip structure in which an insulating film is employed.
The chip-on-chip structure includes a first semiconductor chip 411 and a second semiconductor chip 417. Between the first semiconductor chip 411 and the second semiconductor chip 417, an insulating film 414 is interposed. The insulating film 414 includes a structure that an interconnect pattern 416 and an interconnect pattern 420 is provided in the film 415.
The interconnect pattern 416 is provided with a connection portion 423 at a lower surface thereof. The connection portion 423 is connected to a bump 413a of the first semiconductor chip 412, formed on a surface 412 of the first semiconductor chip. The interconnect pattern 416 is also provided with a connection portion 424 on an upper surface thereof. The connection portion 424 is connected to a bump 419a of the second semiconductor chip, located on a surface 418 of the second semiconductor chip.
The interconnect pattern 420 is provided with a connection portion 427 at a lower surface thereof. The connection portion 427 is connected to a bump 413c of the first semiconductor chip, located on a surface 412 of the first semiconductor chip. The interconnect pattern 420 is also provided with a connection portion 426 on an upper surface thereof. The connection portion 426 is connected to a bump 419b of the second semiconductor chip, located on a surface 418 of the second semiconductor chip.
According to JP-A Laid Open No. 2000-252408, the described structure enables stacking and connecting semiconductor chips that have a different interval between electrodes or different electrode positions, thereby offering a higher degree of freedom in designing a chip-on-chip type semiconductor device.